View TC1302BIPVUA_8877368.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? 2003-2012 microchip technology inc. ds21333c-page 1 tc1302a/b features ? dual output ldo: -v out1 = 1.5v to 3.3v @ 300 ma -v out2 = 1.5v to 3.3v @ 150 ma ? output voltage (see table 8-1) ? low dropout voltage: -v out1 = 104 mv @ 300 ma typical -v out2 = 150 mv @ 150 ma typical ? low supply current: 116 a typical tc1302a/b with both output voltages available ? reference bypass input for low-noise operation ? both output voltages stable with a minimum of 1 f ceramic output capacitor ? separate v out1 and v out2 shdn pins ( tc1302b ) ? power-saving shutdown mode of operation ? wake-up from shdn : 5.3 s. typical ? small 8-pin dfn or msop package options ? operating junction temperature range: - -40c to +125c ? overtemperature and overcurrent protection applications ? cellular/gsm/phs phones ? battery-operated systems ? hand-held medical instruments ? portable computers/pdas ? linear post-regulators for smps ? pagers related literature ? an765, ?using microchip?s micropower ldos?, ds00765, microchip technology inc., 2002 ? an766, ?pin-compatible cmos upgrades to bipolar ldos?, ds00766, microchip technology inc., 2002 ? an792, ?a method to determine how much power a sot23 can dissipate in an application?, ds00792, microchip technology inc., 2001 description the tc1302a/b combines two low dropout (ldo) regulators into a single 8-pin msop or dfn package. both regulator outputs feature low dropout voltage, 104 mv @ 300 ma for v out1 , 150 mv @ 150 ma for v out2 , low quiescent current consumption, 58 a each and a typical regulation accuracy of 0.5%. several fixed-output voltage combinations are available. a reference bypass pin is available to further reduce output noise and improve the power supply rejection ratio of both ldos. the tc1302a/b is stable over all line and load conditions, with a minimum of 1 f of ceramic output capacitance, and utilizes a unique compensation scheme to provide fast dynamic response to sudden line voltage and load current changes. additional features include an overcurrent limit and overtemperature protection that combine to provide a robust design for all load fault conditions. package types 8-pin dfn/msop nc shdn2 bypass gnd nc 1 2 3 45 6 7 8 v out2 v in 1 2 3 4 5 6 7 8 v out1 tc1302a nc shdn2 bypass gnd nc v out2 v in v out1 dfn8 msop8 nc shdn2 bypass gnd shdn1 1 2 3 45 6 7 8 v out2 v in 1 2 3 4 5 6 7 8 v out1 tc1302b nc shdn2 bypass gnd shdn1 v out2 v in v out1 dfn8 msop8 low quiescent current dual output ldo
tc1302a/b ds21333c-page 2 ? 2003-2012 microchip technology inc. functional block diagrams typical application circuits ldo #2 150 ma ldo #1 300 ma ldo #2 150 ma v in v out1 v out2 bandgap reference shdn2 gnd bypass tc1302a tc1302b v in shdn2 gnd bypass shdn1 ldo #1 300 ma bandgap reference v out1 v out2 1.2v 1.2v 8 4 1 2 3 nc gnd nc battery c out1 1f ceramic x5r c in 1f tc1302a c out2 1f ceramic x5r c bypass (note) 10 nf ceramic bypass v in 7 2.7v to 4.2v v out2 6 shdn2 on/off control v out2 2.8v @ 300 ma 2.6v @ 150 ma 5 v out1 8 4 1 2 3 nc gnd shdn1 battery c out1 1f ceramic x5r c in 1f tc1302b c out2 1f ceramic x5r bypass v in 7 2.7v to 4.2v v out2 6 shdn2 on/off control v out2 2.8v @ 300 ma 2.6v @ 150 ma 5 on/off control v out1 note: c bypass is optional v out1
? 2003-2012 microchip technology inc. ds21333c-page 3 tc1302a/b 1.0 electrical characteristics absolute maximum ratings ? v dd ...................................................................................6.5v maximum voltage on any pin ...... (v ss ? 0.3) to (v in + 0.3)v power dissipation ..........................internally limited (note 7) storage temperature .....................................-65c to +150c maximum junction temperature, t j ........................... +150c continuous operating temperature range ..-40c to +125c esd protection on all pins, hbm, mm ?????????????????????? 4 kv, 400v ? notice: stresses above those lis ted under ?maximum rat- ings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this spec ification is not implied. expo- sure to maximum rating conditions for extended periods may affect device reliability. dc characteristics electrical specifications: unless otherwise noted, v in = v r +1v, i out1 = i out2 = 100 a, c in = 4.7 f, c out1 = c out2 = 1 f, c bypass = 10 nf, shdn > v ih , t a = +25c. boldface type specifications apply for juncti on temperatures of -40c to +125c. parameters sym min typ max units conditions input operating voltage v in 2.7 ? 6.0 v note 1 maximum output current i out1max 300 ?? mav in = 2.7v to 6.0v (note 1) maximum output current i out2max 150 ?? mav in = 2.7v to 6.0v (note 1) output voltage tolerance (v out1 and v out2 ) v out v r ? 2.5 v r 0.5 v r + 2.5 % note 2 temperature coefficient (v out1 and v out2 ) tcv out ? 25 ? ppm/c note 3 line regulation (v out1 and v out2 ) ? v out / ? v in ?0.02 0.2 %/v (v r + 1v) ? v in ? 6v load regulation, v out ? 2.5v (v out1 and v out2 ) ? v out ? v out -1 0.1 +1 %i outx = 0.1 ma to i outmax , (note 4) load regulation, v out < 2.5v (v out1 and v out2 ) ? v out ? v out -1.5 0.1 +1.5 %i outx = 0.1 ma to i outmax , (note 4) thermal regulation ? v out / ? p d ?0.04? %/w note 5 dropout voltage (note 6) v out1 > 2.7v v in ? v out ? 104 180 mv i out1 = 300 ma v out2 > 2.6v v in ? v out ? 150 250 mv i out2 = 150 ma supply current tc1302a i in(a) ? 103 180 a shdn2 = v in , i out1 = i out2 = 0 ma tc1302b i in(b) ?114 180 a shdn1 = shdn2 = v in , i out1 = i out2 = 0 ma note 1: the minimum v in has to meet two conditions: v in ? 2.7v and v in ? v r + v dropout . 2: v r is defined as the higher of the tw o regulator nominal output voltages (v out1 or v out2 ). 3: tcv out = ((v outmax - v outmin ) * 10 6 )/(v out * ? t). 4: regulation is measured at a constant ju nction temperature using low duty-cycle pulse testing. load regulation is tested over a load range from 0.1 ma to the maximum specified output current. changes in output voltage due to heating effects are covered by the thermal regulation specification. 5: thermal regulation is defined as the change in output voltage at a time t after a change in power dissipation is applied, excluding load or line regulation effects. specif ications are for a current pulse equal to i lmax at v in = 6v for t = 10 msec. 6: dropout voltage is defined as the input-to-output voltage diff erential at which the output voltage drops 2% below its value measured at a 1v differential. 7: the maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air (i.e., t a , t j , ? ja ). exceeding the maximum allowable power dissipation causes the device to initiate thermal shutdown.
tc1302a/b ds21333c-page 4 ? 2003-2012 microchip technology inc. temperature specifications shutdown supply current tc1302a i in_shdn a ?58 90 a shdn2 = gnd shutdown supply current tc1302b i in_shdn b ? 0.1 1 a shdn1 = shdn2 = gnd power supply rejection ratio psrr ? 58 ? db f ? 100 hz, i out1 = i out2 = 50 ma, c in = 0 f output noise en ? 830 ? nv/(hz) ? f ? 1khz, i out1 = i out2 = 50 ma, c in = 0 f output short circuit current (average) v out1 i outsc1 ? 200 ? ma r load1 ? 1 ? v out2 i outsc2 ? 140 ? ma r load2 ? 1 ? shdn input high threshold v ih 45 ??%v in v in = 2.7v to 6.0v shdn input low threshold v il ?? 15 %v in v in = 2.7v to 6.0v wake up time (from shdn mode), (v out2 ) t wk ?5.320 sv in = 5v, i out1 = i out2 = 30 ma, see figure 5-1 settling time (from shdn mode), (v out2 ) t s ?50? sv in = 5v, i out1 = i out2 = 50 ma, see figure 5-2 thermal shutdown die temperature t sd ? 150 ? c v in = 5v, i out1 = i out2 = 100 a thermal shutdown hysteresis t hys ?10? cv in = 5v electrical specifications: unless otherwise indicated, all limits are specified for: v in = +2.7v to +6.0v. parameters sym min typ max units conditions temperature ranges operating junction temperature range t a -40 ? +125 c steady state storage temperature range t a -65 ? +150 c maximum junction temperature t j ? ? +150 c transient thermal package resistances thermal resistance, msop8 ? ja ? 208 ? c/w typical 4-layer board thermal resistance, dfn8 ? ja ? 41 ? c/w typical 4-layer board with vias dc characteristics (continued) electrical specifications: unless otherwise noted, v in = v r +1v, i out1 = i out2 = 100 a, c in = 4.7 f, c out1 = c out2 = 1 f, c bypass = 10 nf, shdn > v ih , t a = +25c. boldface type specifications apply for juncti on temperatures of -40c to +125c. parameters sym min typ max units conditions note 1: the minimum v in has to meet two conditions: v in ? 2.7v and v in ? v r + v dropout . 2: v r is defined as the higher of the tw o regulator nominal output voltages (v out1 or v out2 ). 3: tcv out = ((v outmax - v outmin ) * 10 6 )/(v out * ? t). 4: regulation is measured at a constant ju nction temperature using low duty-cycle pul se testing. load regulation is tested over a load range from 0.1 ma to the maximum specified output current. changes in output voltage due to heating effects are covered by the thermal regulation specification. 5: thermal regulation is defined as the change in output voltage at a time t after a change in power dissipation is applied, excluding load or line regulation effects. specif ications are for a current pulse equal to i lmax at v in = 6v for t = 10 msec. 6: dropout voltage is defined as the input-to-output voltage diff erential at which the output voltage drops 2% below its value measured at a 1v differential. 7: the maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air (i.e., t a , t j , ? ja ). exceeding the maximum allowable power dissipation causes the device to initiate thermal shutdown.
? 2003-2012 microchip technology inc. ds21333c-page 5 tc1302a/b 2.0 typical performance curves note: unless otherwise indicated, v in = v r +1v, i out1 = i out2 = 100 a, c in = 4.7 f, c out1 = c out2 = 1 f (x5r or x7r), c bypass = 0 pf, shdn1 = shdn2 > v ih , t a = +25c. figure 2-1: quiescent current vs. input voltage. figure 2-2: s hdn voltage threshold vs. input voltage. figure 2-3: quiescent current vs. junction temperature. figure 2-4: output voltage vs. input voltage. figure 2-5: output voltage vs. input voltage. figure 2-6: dropout voltage vs. output current (v out1 ). note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 0 50 100 150 200 250 300 350 2.73.03.33.63.94.24.54.85.15.45.76.0 input voltage (v) quiescent current (a) v out2 shdn v out2 active t j = +25c i out1 = i out2 = 0 a v out1 active tc1302b 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 2.7 3 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 6 input voltage (v) shdn threshold (v) on off 40 50 60 70 80 90 100 110 120 130 140 -40 -25 -10 5 20 35 50 65 80 95 110 125 junction temperature (c) quiescent current (a) v in = 4.2v i out1 = i out2 = 0 a v out1 active v out2 shdn v out2 active tc1302b 2.60 2.70 2.80 2.90 3.00 2.7 3 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 6 input voltage (v) output voltage (v) t j = +25c i out1 = 100 ma i out2 = 50 ma v out1 v out2 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90 2.7 3 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 6 input voltage (v) output voltage (v) t j = +25c i out1 = 300 ma i out2 = 100 ma v out1 v out2 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0 0 50 100 150 200 250 300 i out1 (ma) dropout voltage v out1 (mv) v r1 = 2.8v v r2 = 2.6v i out2 = 100 a t j = - 40c t j = +25c t j = +125c
tc1302a/b ds21333c-page 6 ? 2003-2012 microchip technology inc. note: unless otherwise indicated, v in = v r +1v, i out1 = i out2 = 100 a, c in = 4.7 f, c out1 = c out2 = 1 f (x5r or x7r), c bypass = 0 pf, shdn1 = shdn2 > v ih , t a = +25c. figure 2-7: dropout voltage vs. junction temperature (v out1 ). figure 2-8: dropout voltage vs. output current (v out2 ). figure 2-9: dropout voltage vs. junction temperature (v out2 ). figure 2-10: v out1 and v out2 load regulation vs. junction temperature. figure 2-11: v out1 and v out2 line regulation vs. junction temperature. figure 2-12: v out1 vs. junction temperature. 0 20 40 60 80 100 120 140 -40 -25 -10 5 20 35 50 65 80 95 110 125 junction temperature (c) dropout voltage v out1 (mv) v r1 = 2.8v v r2 = 2.6v i out2 = 100 a i out1 = 300 ma i out1 = 100 ma i out1 = 50 ma 0 20 40 60 80 100 120 140 160 180 0 30 60 90 120 150 i out2 (ma) dropout voltage, v out2 (mv) v r1 = 2.8v v r2 = 2.6v i out1 = 100 a t j = +125c t j = +25c t j = - 40c 0 20 40 60 80 100 120 140 160 180 -40 -25 -10 5 20 35 50 65 80 95 110 125 junction temperature (c) dropout voltage v out2 (mv) v r1 = 2.8v v r2 = 2.6v i out1 = 100 a i out2 = 150 ma i out2 = 50 ma i out2 = 10 ma -0.40 -0.30 -0.20 -0.10 0.00 0.10 0.20 0.30 0.40 -40 -25 -10 5 20 35 50 65 80 95 110 125 junction temperature (125c) load regulation (%) i out2 = 0.1 ma to 150 ma i out1 = 0.1 ma to 300 ma v r1 = 2.8v v r2 = 2.6v v in = 4.2 v out2 v out1 0.000 0.005 0.010 0.015 0.020 0.025 0.030 0.035 0.040 0.045 -40 -25 -10 5 20 35 50 65 80 95 110 125 junction temperature (c) line regulation (%/v) v in = 3.8v to 6.0v v r1 = 2.8v, i out1 = 100 a v r2 = 2.6v, i out2 = 100 a v out1 v out2 2.808 2.812 2.816 2.820 2.824 2.828 2.832 -40 -25 -10 5 20 35 50 65 80 95 110 125 junction temperature (c) output voltage v out1 (v) v in = 4.2v v r1 = 2.8v v r2 = 2.6v, i out2 = 100 a i out1 = 300 ma i out1 = 100 a i out1 = 100 ma
? 2003-2012 microchip technology inc. ds21333c-page 7 tc1302a/b note: unless otherwise indicated, v in = v r +1v, i out1 = i out2 = 100 a, c in = 4.7 f, c out1 = c out2 = 1 f (x5r or x7r), c bypass = 0 pf, shdn1 = shdn2 > v ih , t a = +25c. figure 2-13: v out1 vs. junction temperature. figure 2-14: v out2 vs. junction temperature. figure 2-15: v out2 vs. junction temperature. figure 2-16: power supply rejection ratio vs. frequency (without bypass capacitor). figure 2-17: power supply rejection ratio vs. frequency (with bypass capacitor). figure 2-18: v out1 and v out2 noise vs. frequency (without bypass capacitor). 2.808 2.816 2.824 2.832 2.840 2.848 2.856 -40 -25 -10 5 20 35 50 65 80 95 110 125 junction temperature (c) output voltage v out1 (v) v r1 = 2.8v, i out1 = 300 ma v r2 = 2.6v, i out2 = 100 a v in = 6.0v v in = 4.2v v in = 3.0v 2.615 2.620 2.625 2.630 2.635 2.640 2.645 -40 -25 -10 5 20 35 50 65 80 95 110 125 junction temperature (c) output voltage v out2 (v) v in = 4.2v v r1 = 2.8v, i out1 = 100 a v r2 = 2.6v i out2 = 150 ma i out2 = 100 a i out2 = 50 ma 2.624 2.628 2.632 2.636 2.640 2.644 -40 -25 -10 5 20 35 50 65 80 95 110 125 junction temperature (c) output voltage v out2 (v) v r1 = 2.8v, i out1 = 100 a v r2 = 2.6v, i out2 = 150 ma v in = 6.0v v in = 3.0v v in = 4.2v 0.01 0.1 1 10 0.01 0.1 1 10 100 1000 frequency (khz) noise (v/ hz) v in = 4.2v v r1 = 2.8v v r2 =2.6v i out1 = 150 ma i out2 = 100 ma c bypass = 0 nf v out1 v out2
tc1302a/b ds21333c-page 8 ? 2003-2012 microchip technology inc. note: unless otherwise indicated, v in = v r +1v, i out1 = i out2 = 100 a, c in = 4.7 f, c out1 = c out2 = 1 f (x5r or x7r), c bypass = 0 pf, shdn1 = shdn2 > v ih , t a = +25c. figure 2-19: v out1 and v out2 noise vs. frequency (with bypass capacitor). figure 2-20: v out1 and v out2 power-up from shutdown tc1302b. figure 2-21: v out2 power-up from shutdown input tc1302a. figure 2-22: v out1 and v out2 power-up from input voltage tc1302b. figure 2-23: dynamic line response. figure 2-24: 300 ma dynamic load step v out1 . 0.001 0.01 0.1 1 10 0.01 0.1 1 10 100 1000 frequency (khz) noise (v/ hz) v in = 4.2v v r1 = 2.8v v r2 =2.6v i out1 = 150 ma i out2 = 100 ma c bypass = 10 nf v out1 v out2
? 2003-2012 microchip technology inc. ds21333c-page 9 tc1302a/b note: unless otherwise indicated, v in = v r +1v, i out1 = i out2 = 100 a, c in = 4.7 f, c out1 = c out2 = 1 f (x5r or x7r), c bypass = 0 pf, shdn1 = shdn2 > v ih , t a = +25c. figure 2-25: 150 ma dynamic load step v out2 .
tc1302a/b ds21333c-page 10 ? 2003-2012 microchip technology inc. 3.0 tc1302a pin descriptions the descriptions of the pins are listed in table 3-1. table 3-1: tc1302a pin function table 3.1 regulated output voltage #1 (v out1 ) connect v out1 to the positive side of the v out1 capacitor and load. capable of 300 ma maximum output current. v out1 output is available when v in is available; there is no pin to turn it off . see tc1302b if on/off control of v out1 is desired. 3.2 circuit ground pin (gnd) connect gnd to the negative side of the input and output capacitor. only the ldo internal circuitry bias current flows out of this pin (200 a maximum). 3.3 reference bypass input by connecting an external 10 nf capacitor (typical) to the bypass input, both outputs (v out1 and v out2 ) will have less noise and improved power supply ripple rejection (psrr) performance. the ldo output voltage start-up time will increase with the addition of an external bypass capacitor. by leaving this pin unconnected, the start-up time will be minimized. 3.4 output voltage #2 shutdown (shdn2 ) on/off control is performed by connecting shdn2 to its proper level. when the input of this pin is connected to a voltage less than 15% of v in , v out2 will be off . if this pin is connected to a voltage that is greater than 45% of v in , v out2 will be turned on. 3.5 regulated output voltage #2 (v out2 ) connect v out2 to the positive side of the v out2 capacitor and load. this pin is capable of a maximum output current of 150 ma. v out2 can be turned on and off using shdn2 . 3.6 unregulated input voltage pin (v in ) connect the unregulated input voltage source to v in . if the input voltage source is located more than several inches away or is a battery, a typical input capacitance of 1 f to 4.7 f is recommended. pin no. name function 1 nc no connect. 2v out1 regulated output voltage #1, capable of 300 ma. 3 gnd circuit ground pin. 4 bypass internal reference bypass pin. a 10 nf external capacitor can be used to further reduce output noise and improve psrr performance. 5 shdn2 output #2 shutdown control input. 6v out2 regulated output voltage #2, capable of 150 ma. 7v in unregulated input voltage pin. 8 nc no connect.
? 2003-2012 microchip technology inc. ds21333c-page 11 tc1302a/b 4.0 tc1302b pin descriptions the descriptions of the pins are listed in table 4-1. table 4-1: tc1302b pin function table 4.1 regulated output voltage #1 (v out1 ) connect v out1 to the positive side of the v out1 capacitor and load. capable of 300 ma maximum output current. for the tc1302b, v out1 can be turned on and off using the shdn1 input pin. 4.2 circuit ground pin (gnd) connect gnd to the negative side of the input and output capacitor. only the ldo internal circuitry bias current flows out of this pin (200 a maximum). 4.3 reference bypass input by connecting an external 10 nf capacitor (typical) to the bypass input, both outputs (v out1 and v out2 ) will have less noise and improved power supply ripple rejection (psrr) performance. the ldo output voltage startup time will increase with the addition of an external bypass capacitor. by leaving this pin unconnected, the startup time will be minimized. 4.4 output voltage #2 shutdown (shdn2 ) on/off control is performed by connecting shdn2 to its proper level. when this pin is connected to a voltage less than 15% of v in , v out2 will be off . if this pin is connected to a voltage that is greater than 45% of v in , v out2 will be turned on. 4.5 regulated output voltage #2 (v out2 ) connect v out2 to the positive side of the v out2 capacitor and load. this pin is capable of a maximum output current of 150 ma. v out2 can be turned on and off using shdn2 . 4.6 unregulated input voltage pin (v in ) connect the unregulated input voltage source to v in . if the input voltage source is located more than several inches away, or is a battery, a typical minimum input capacitance of 1 f and 4.7 f is recommended. 4.7 output voltage #1 shutdown (shdn1 ) on/off control is performed by connecting sndn1 to its proper level. when this pin is connected to a voltage less than 15% of v in , v out1 will be off . if this pin is connected to a voltage that is greater than 45% of v in , v out1 will be turned on. pin no. name function 1 nc no connect. 2v out1 regulated output voltage #1, capable of 300 ma. 3 gnd circuit ground pin. 4 bypass internal reference bypass pin. a 10 nf external capacitor can be used to further reduce output noise and improve psrr performance. 5 shdn2 output #2 shutdown control input. 6v out2 regulated output voltage #2, capable of 150 ma. 7v in unregulated input voltage pin. 8 shdn1 output #1 shutdown control input.
tc1302a/b ds21333c-page 12 ? 2003-2012 microchip technology inc. 5.0 detailed description 5.1 device overview the tc1302a/b is a combination device consisting of one 300 ma ldo regulator with a fixed output voltage v out1 (1.5v ? 3.3v) and one 150 ma ldo regulator with a fixed output voltage v out2 (1.5v ? 3.3v). for the tc1302a, the 300 ma output (v out1 ) is always present, independent of the level of shdn2 . the 150 ma output (v out2 ) can be turned on/off by controlling the level of shdn2 . for the tc1302b, v out1 and v out2 each have independent shutdown input pins (shdn1 and shdn2) to control their respective outputs. 5.2 ldo output #1 ldo output #1 is rated for 300 ma of output current. the typical dropout voltage for v out1 = 104 mv @ 300 ma. a 1 f (minimum) output capacitor is needed for stability and should be located as close to the v out1 pin and ground as possible. 5.3 ldo output #2 ldo output #2 is rated for 150 ma of output current. the typical dropout voltage for v out2 = 150mv. a 1f (minimum) capacitor is needed for stability and should be located as close to the v out2 pin and ground as possible. 5.4 input capacitor low input source impedance is necessary for the two ldo outputs to operate properly. when operating from batteries, or in applications with long lead length (> 10 inches) between the input source and the ldo, some input capacitance is recommended. a minimum of 1.0 f to 4.7 f is recommended for most applications. when using large capacitors on the ldo outputs, larger capacitance is recommended on the ldo input. the capacitor should be placed as close to the input of the ldo as is practical. larger input capacitors will help reduce the input impedance and further reduce any high-frequency noise on the input and output of the ldo. 5.5 output capacitor a minimum output capacitance of 1 f for each of the tc1302a/b ldo outputs is necessary for stability. ceramic capacitors are recommended because of their size, cost and environmental robustness qualities. tantalum or aluminum electrolytic capacitors can be used on the ldo outputs as well. the equivalent series resistance (esr) requirements on the electrolytic output capacitor?s are between 0 and 2 ohms. the output capacitor should be located as close to the ldo output as is practical. ceramic materials, x7r and x5r, have low temperature coefficients and are well within the acceptable esr range required. a typical 1 uf x5r 0805 capacitor has an esr of 50 milli- ohms. larger ldo output capacitors can be used with the tc1302a/b to improve dynamic performance and power supply ripple rejection performance. a maximum of 10 f is recommended. aluminum electrolytic capacitors are not recommended for low temperature applications of < -25 c. 5.6 bypass input the bypass pin is connected to the internal ldo reference. by adding capacitance to this pin, the ldo ripple rejection, input voltage transient response and output noise performance are all increased. a typical bypass capacitor between 470 pf to 10 nf is recommended. larger bypass capacitors can be used, but result in a longer time period for the ldo outputs to reach their rated output voltage when started from shdn or v in . 5.7 gnd for the optimal noise and psrr performance, the gnd pin of the tc1302a/b should be tied to a quiet circuit ground. for applications that have switching or noisy inputs, tie the gnd pin to the return of the output capacitor. ground planes help lower inductance and voltage spikes caused by fast transient load currents and are recommended for applications that are subjected to fast load transients. 5.8 shdn1 /s hdn2 operation the tc1302a shdn2 pin is used to turn v out2 on and off . a logic-high level on shdn2 will enable the v out2 output, while a logic-low on the shdn2 pin will disable the v out2 output. for the tc1302a, v out1 is not affected by shdn2 and will be enabled as long as the input voltage is present. the tc1302b shdn1 and shdn2 pins are used to turn v out1 and v out2 on and off . they operate independent of each other.
? 2003-2012 microchip technology inc. ds21333c-page 13 tc1302a/b 5.9 tc1302a shdn2 timing v out1 will rise independent of the level of shdn2 for the tc1302a. figure 5-1 is used to define the wake-up time from shutdown (t wk ) and the settling time (t s ). the wake-up time is dependant upon the frequency of operation. the faster the shdn pin is pulsed, the shorter the wake-up time will be. figure 5-1: tc1302a timing. 5.10 tc1302b shdn1 /s hdn2 timing for the tc1302b, the shdn1 input pin is used to control v out1 . the shdn2 input pin is used to control v out2 , independent of the logic input on shdn1 . figure 5-2: tc1302b timing. 5.11 device protection 5.11.1 overcurrent limit in the event of a faulted output load, the maximum current the ldo output will permit to flow is limited internally for each of the tc1302a/b outputs. the peak current limit for v out1 is typically 1.1a, while the peak current limit for v out2 is typically 0.5a. during short- circuit operation, the average current is limited to 200 ma for v out1 and 140 ma for v out2 . 5.11.2 overtemperature protection if the internal power dissipation within the tc1302a/b is excessive due to a faulted load or higher-than- specified line voltage, an internal temperature-sensing element will prevent the junction temperature from exceeding approximately 150 c. if the junction temperature does reach 150 c, both outputs will be disabled until the junction temperature cools to approximately 140 c and the device resumes normal operation. if the internal power dissipation continues to be excessive, the device will again shut off. v in shdn2 v out1 v out2 t wk t s shdn2 shdn1 v in v out1 t wk t s v out2
tc1302a/b ds21333c-page 14 ? 2003-2012 microchip technology inc. 6.0 application circuits/ issues 6.1 typical application the tc1302a/b is used for applications that require the integration of two ldos. figure 6-1: typical application circuit tc1302a/b. 6.1.1 application input conditions 6.2 power calculations 6.2.1 power dissipation the internal power dissipation within the tc1302a/b is a function of input voltage, output voltage, output current and quiescent current. the following equation can be used to calculate the internal power dissipation for each ldo. equation 6-1: in addition to the ldo pass element power dissipation, there is power dissipation within the tc1302a/b as a result of quiescent or ground current. the power dissipation, as a result of the ground current, can be calculated using the following equation. equation 6-2: the total power dissipated within the tc1302a/b is the sum of the power dissipated in both of the ldos and the p(i gnd ) term. because of the cmos construction, the typical i gnd for the tc1302a/b is 116 a. operating at a maximum of 4.2v results in a power dissipation of 0.5 milliwatts. for most applications, this is small compared to the ldo pass device power dissi- pation and can be neglected. the maximum continuous operating junction temperature specified for the tc1302a/b is +125 c . to estimate the internal junction temperature of the tc1302a/b, the total internal power dissipation is multiplied by the thermal resistance from junction to ambient (r ? ja ) of the device. the thermal resistance from junction-to-ambient for the 3x3dfn8 pin package is estimated at 41 c/w. equation 6-3: package type = 3x3dfn8 input voltage range = 2.7v to 4.2v v in maximum = 4.2v v in typical = 3.6v v out1 = 300 ma maximum v out2 = 150 ma maximum 8 4 1 2 3 nc gnd nc battery c out1 1f ceramic x5r c in 1f tc1302a c out2 1 f ceramic x5r c bypass 10 nf ceramic bypass v in 7 2.7v to 4.2v v out2 6 shdn2 on/off control v out2 2.8v @ 300 ma 1.8v 5 v out1 8 4 1 2 3 nc battery c out1 1f ceramic x5r c in 1f tc1302b c out2 1f ceramic x5r bypass v in 7 2.7v to 4.2v v out2 6 shdn2 on/off control v out2 2.8v @ 300 ma 1.8v 5 on/off control v out1 v out1 @ 150 ma gnd @ 150 ma s hdn1 p ldo v in max ? ?? v out min ?? ? ?? i out max ? ?? ? = p ldo = ldo pass device internal power dissipation v in(max) = maximum input voltage v out(min) = ldo minimum output voltage p ignd ?? v in max ?? i vin ? = p i(gnd) = total current in ground pin. v in(max) = maximum input voltage. i vin = current flowing in the v in pin with no output current on either ldo output. t jmax ?? p total r ? ja ? t amax + = t j(max) = maximum continuous junction temperature. p total = total device power dissipation. r ? ja = thermal resistance from junction to ambient. t amax = maximum ambient temperature.
? 2003-2012 microchip technology inc. ds21333c-page 15 tc1302a/b the maximum power dissipation capability for a package can be calculated given the junction-to- ambient thermal resistance and the maximum ambient temperature for the application. the following equation can be used to determine the package maximum internal power dissipation. equation 6-4: equation 6-5: equation 6-6: 6.3 typical application internal power dissipation, junction temperature rise, junction temperature and maximum power dissipation are calculated in the following example. the power dissipation, as a result of ground current, is small enough to be neglected. 6.3.1 power dissipation example device junction temperature rise the internal junction temperature rise is a function of internal power dissipation and the thermal resistance from junction to ambient for the application. the thermal resistance from junction to ambient (r ? ja ) is derived from an eia/jedec standard for measuring thermal resistance for small surface-mount packages. the eia/jedec specification is jesd51-7 ?high effective thermal conductivity test board for leaded surface mount packages?. the standard describes the test method and board specifications for measuring the thermal resistance from junction to ambient. the actual thermal resistance for a particular application can vary depending on many factors, such as copper area and thickness. refer to an792, ?a method to determine how much power a sot23 can dissipate in an application?, (ds00792), for more information regarding this subject. junction temperature estimate to estimate the internal junction temperature, the calculated temperature rise is added to the ambient or offset temperature. for this example, the worst-case junction temperature is estimated below. maximum package power dissipation at 50c ambient temperature package package type = 3x3dfn8 input voltage v in = 2.7v to 4.2v ldo output voltages and currents v out1 = 2.8v i out1 =300ma v out2 = 1.8v i out2 =150ma p dmax ?? t jmax ?? t amax ?? ? ?? r ? ja --------------------------------------------------- = p d(max) = maximum device power dissipation. t j(max) = maximum continuous junction temperature. t a(max) = maximum ambient temperature. r ? ja = thermal resistance from junction to ambient. t jrise ?? p dmax ?? r ? ja ? = t j(rise) = rise in device junction temperature over the ambient temperature. p d(max) = maximum device power dissipation. r ? ja = thermal resistance from junction-to- ambient. t j t jrise ?? t a + = t j = junction temperature. t j(rise) = rise in device junction temperature over the ambient temperature. t a = ambient temperature. maximum ambient temperature t a(max) =50c internal power dissipation internal power dissipation is the sum of the power dissipation for each ldo pass device. p ldo1(max) =(v in(max) - v out1(min) ) x i out1(max) p ldo1 = (4.2v - (0.975 x 2.8v)) x 300 ma p ldo1 = 441.0 milliwatts p ldo2 = (4.2v - (0.975 x 1.8v)) x 150 ma p ldo2 = 366.8 milliwatts p total =p ldo1 + p ldo2 p total = 807.8 milliwatts t j(rise) =p total x rq ja t jrise = 807.8 milliwatts x 41.0 c/w t jrise =33.1 c t j =t jrise + t a(max) t j = 83.1c 3x3dfn8 (41c/watt r ? ja ) p d(max) = (125c - 50c)/41 c/w p d(max) = 1.83 watts msop8 (208c/watt r ? ja ) p d(max) = (125c - 50c)/208 c/w p d(max) = 0.360 watts
tc1302a/b ds21333c-page 16 ? 2003-2012 microchip technology inc. 7.0 typical layout figure 7-1: msop8 silk-screen layer. when designing the physical layout for the tc1302a/b, the highest priority should be placed on positioning the input and output capacitors as close to the device pins as is practical. figure 7-1 above represents a typical placement of the components when using the smt0805 capacitors. figure 7-2: dfn3x3 silk-screen example. figure 7-2 above represents a typical placement of the components when using the smt0603 capacitors. 8.0 additional output voltages 8.1 output voltage options table 8-1 describes the range of output voltage options available for the tc1302a/b. v out1 and v out2 can be factory preset from 1.5v to 3.3v in 100 mv increments. table 8-1: custom output voltages for a listing of tc1302a/b standard parts, refer to the product identification system on page 23. v out1 v out2 1.5v to 3.3v 1.5v to 3.3v
? 2003-2012 microchip technology inc. ds21333c-page 17 tc1302a/b 9.0 packaging information 9.1 package marking information x1 represents v out1 configuration: x2 represents v out2 configuration: for a listing of tc1302a/b standard parts, refer to the product identification system on page 23. 8-lead msop xxxxxx ywwnnn example: bfh 0542 256 example: 32afh 542256 8-lead dfn xxxx yyww nnn ? 32a = tc1302a ? f = 2.8v v out1 ? h = 2.6v v out2 code v out1 code v out1 code v out1 a3.3vj2.4vs1.5v b3.2vk2.3vt1.65v c 3.1v l 2.2v u 2.85v d 3.0v m 2.1v v 2.65v e 2.9v n 2.0v w 1.85v f2.8vo1.9vx ? g2.7vp1.8vy ? h2.6vq1.7vz ? i2.5vr1.6v code v out2 code v out1 code v out2 a 3.3v j 2.4v s 1.5v b 3.2v k 2.3v t 1.65v c 3.1v l 2.2v u 2.85v d 3.0v m 2.1v v 2.65v e 2.9v n 2.0v w 1.85v f2.8vo1.9vx ? g2.7vp1.8vy ? h2.6vq1.7vz ? i2.5vr1.6v legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e
tc1302a/b ds21333c-page 18 ? 2003-2012 microchip technology inc. 8-lead plastic micro small outline package (ua) (msop) d a a1 l c (f) a2 e1 e p b n 1 2 dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not .037 ref f footprint (reference) exceed .010" (0.254mm) per side. notes: drawing no. c04-111 *controlling parameter mold draft angle top mold draft angle bottom foot angle lead width lead thickness c b .003 .009 .006 .012 dimension limits overall height molded package thickness molded package width overall length foot length standoff overall width number of pins pitch a l e1 d a1 e a2 .016 .024 .118 bsc .118 bsc .000 .030 .193 typ. .033 min p n units .026 bsc nom 8 inches 0.95 ref - - .009 .016 0.08 0.22 0 0.23 0.40 8 millimeters* 0.65 bsc 0.85 3.00 bsc 3.00 bsc 0.60 4.90 bsc .043 .031 .037 .006 0.40 0.00 0.75 min max nom 1.10 0.80 0.15 0.95 max 8 -- - 15 5 - 15 5 - jedec equivalent: mo-187 0 - 8 5 5 - - 15 15 - - - - note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2003-2012 microchip technology inc. ds21333c-page 19 tc1302a/b 8-lead plastic dual flat no lead package (mf) 3x3x0.9 mm body (dfn) e2 d dimensions d and e do not include mold flash or protrusions. mold flash or protrusions shall not exposed pad width exposed pad length lead length *controlling parameter lead width drawing no. c04-062 notes: exposed pad dimensions vary with paddle size. exceed .010" (0.254mm) per side. overall width d2 e2 l b d .019 .012 .007 .047 .055 .010 .118 bsc a1 number of pins standoff lead thickness overall length overall height pitch a a3 p n units a a1 e a3 dimension limits 8 .000 .001 .008 ref. .118 bsc .031 .026 bsc min inches nom top view exposed metal pad 0.48 0.26 3.00 bsc 0.30 .022 .069 .015 .096 0.23 1.20 1.39 0.55 0.37 1.75 2.45 0.02 0.80 3.00 bsc 0.20 ref. 0.65 bsc millimeters* .002 .039 0.00 min max nom 8 0.05 1.00 max bottom view 2 1 id index pin 1 e l d2 p b n 3. 4. package may have one or more exposed tie bars at ends. 1. area pin 1 visual index feature may vary, but must be located within the hatched area. 2. (note 2) tie bar (note 1) exposed 0.90 .035 (note 4) (note 4) 5. jedec equivalent: pending note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
tc1302a/b ds21333c-page 20 ? 2003-2012 microchip technology inc. notes:
? 2003-2012 microchip technology inc. ds21333c-page 21 tc1302a/b appendix a: revision history revision a (september 2003) original data sheet release. revision b (january 2005) the following is the list of modifications: 1. correct the incorrect part number options shown on the product identification system page and change the ?standard? output voltage and reset voltage combinations. 2. added appendix a: revision history. revision c (november 2012) added a note to each package outline drawing.
tc1302a/b ds21333c-page 22 l ? 2003-2012 microchip technology inc. notes:
? 2003-2012 microchip technology inc. ds21333c-page 23 tc1302a/b product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . device: tc1302a: dual output ldo with single shutdown input. tc1302b: dual output ldo with dual shutdown inputs. standard configurations: * v out1 /v out2 configuration code tc1302a 3.0/1.65 dt tc1302b 3.0/1.65 2.6/1.8 2.5/1.8 dt hp ip * contact factory for alternate output voltage configurations. temperature range: v = -40c to +125c package: mf = dual flat, no lead (3x3 mm body), 8-lead ua = plastic micro small outline (msop), 8-lead tube or tape and reel: blank = tube tr = tape and reel examples: a) tc1302adtvmf: 3.0, 1.65, 8ld dfn pkg. a) tc1302bdtvmf: 3.0, 1.65, 8ld dfn pkg. b) tc1302bhpvmftr: 2.6, 1.8, 8ld dfn pkg, tape and reel. c) TC1302BIPVUA: 2.5, 1.8, 8ld msop pkg. part no. x- x v out1 type a/b tc1302 x v out2 x temp range xx package xx tube or tape & reel standard configurations
tc1302a/b ds21333c-page 24 ? 2003-2012 microchip technology inc. notes:
? 2003-2012 microchip technology inc. ds21333c-page 25 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mtp, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. analog-for-the-digital age, app lication maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, sqi, serial quad i/o, total endurance, tsharc, uniwindriver, wiperlock, zena and z-scale are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. gestic and ulpp are registered trademarks of microchip technology germany ii gmbh & co. & kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2003-2012, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 9781620767443 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
ds21333c-page 26 ? 2003-2012 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://www.microchip.com/ support web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 cleveland independence, oh tel: 216-447-0464 fax: 216-447-0643 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 indianapolis noblesville, in tel: 317-773-8323 fax: 317-773-5453 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8569-7000 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - chongqing tel: 86-23-8980-9588 fax: 86-23-8980-9500 china - hangzhou tel: 86-571-2819-3187 fax: 86-571-2819-3189 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 asia/pacific india - bangalore tel: 91-80-3090-4444 fax: 91-80-3090-4123 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - osaka tel: 81-66-152-7160 fax: 81-66-152-9310 japan - yokohama tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-5778-366 fax: 886-3-5770-955 taiwan - kaohsiung tel: 886-7-213-7828 fax: 886-7-330-9305 taiwan - taipei tel: 886-2-2508-8600 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 worldwide sales and service 10/26/12

▲Up To Search▲

Price & Availability of TC1302BIPVUA

	To Download TC1302BIPVUA Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .